Performance metrics analysis of 4 bit array multiplier circuit using 2 PASCL logic

Multipliers play a key role in today´s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets - high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation. A novel based Two Phase adiabatic static CMOS logic 4 bit array multiplier circuit with low power, low delay, low PDP has been described in this paper. This circuit has been designed and simulated using standard TSMC 0.18μm technology, and compare the results with that of conventional CMOS circuits. It has been observed that power saving up to 36.96% is achieved over conventional CMOS logic at 10 MHz frequency.