An efficient design and comparative analysis of low power memory cell structures

Author

Gavaskar, K. ; Ragupathy, U.S.

Author_Institution

ECE, Kongu Eng. Collezge, Perundurai, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

5

Abstract

With technology scaling, lower power operation has become one of the key areas of importance in VLSI Design. Power reduction in memory circuits with a little compromise on performance is very useful as they form a major part of a digital chip. This paper presents a power analysis model for adiabatic SRAM. The adiabatic SRAM´s and the proposed model power characteristics are simulated, analyzed and compared for various performance frequencies and voltage levels. Simulation results show the power savings that are achieved up to 20% over a frequency range of operation of 10MHz to 200MHz respectively against the static CMOS implementation.

Keywords

CMOS integrated circuits; SRAM chips; VLSI; low-power electronics; VLSI design; adiabatic SRAM; digital chip; frequency 10 MHz to 200 MHz; low power memory cell structures; memory circuits; power reduction; static CMOS implementation; technology scaling; CMOS integrated circuits; Circuit stability; Microprocessors; Power demand; SRAM cells; Transistors; Energy Recovery; IRS scheme; Memory; Stack effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on

Conference_Location

Coimbatore

Type

conf

DOI

10.1109/ICGCCEE.2014.6922280

Filename

6922280