An efficient design and comparative analysis of low power memory cell structures

With technology scaling, lower power operation has become one of the key areas of importance in VLSI Design. Power reduction in memory circuits with a little compromise on performance is very useful as they form a major part of a digital chip. This paper presents a power analysis model for adiabatic SRAM. The adiabatic SRAM´s and the proposed model power characteristics are simulated, analyzed and compared for various performance frequencies and voltage levels. Simulation results show the power savings that are achieved up to 20% over a frequency range of operation of 10MHz to 200MHz respectively against the static CMOS implementation.