Design of low power L2 cache architecture using partial way tag information

Nowadays high-performance microprocessors make use of cache write-through policy for performance improvement and achieving good tolerance to soft errors in on-chip cache. However write through policy incurs large power utilization, while accessing the cache at low level (L2 cache) during write operation. In existing method, way_tagged cache was used under write-through policy, it´s consumed more energy. A new cache architecture has a partial tag enhanced-bloom filter is used to improve the accuracy of cache miss prediction. By maintaining the wag tag of L2 cache in the L1 cache during read operation. The proposed technique enables L2 cache to work in direct mapping manner during write hit and reducing tag comparison of cache miss prediction, if cache miss is predicted there is no need to access the L2 cache. So that significant portion of energy will be reduced, without performance degradation. Simulation results are obtained both L1 and L2 cache configuration. The proposed technique achieves 63% energy saving in L2 cache on average with only 0.02% area overhead and no performance degradation, when compare with existing methods.