Power gating in FinFET Adiabatic circuits

Author

Deo, Nikhil ; Mangang, Rusni Kima ; Murugan, K.

Author_Institution

Dept. of Electron. & Commun. Eng., North Eastern Regional Inst. of Sci. & Technol., Nirjuli, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

5

Abstract

In this paper, we have implemented power gating in FinFET based Adiabatic circuits. Power gating is a low power design technique used in circuits having standby/sleep mode. Again adiabatic logic has very low switching power dissipation than compared to CMOS logic, also when FinFET devices are used in place of MOSFET then power dissipation can be further reduced. So we have used the combination of all these techniques to design low power digital circuits. For validating our idea we designed two power gated adiabatic circuits, first one is IPFAL Inverter and the second one is IPFAL 2:1 Multiplexer using PTM 45nm technology node for bulk MOSFET as well as FinFET.

Keywords

MOSFET; low-power electronics; network synthesis; CMOS logic; FinFET adiabatic circuits; IPFAL 2:1 multiplexer; IPFAL inverter; PTM technology node; bulk MOSFET; low power digital circuit design; power gating; size 45 nm; sleep mode; standby mode; very low switching power dissipation; Clocks; FinFETs; Inverters; Logic gates; Multiplexing; Power dissipation; Adiabatic logic; FinFET; Low power; Power gating;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on

Conference_Location

Coimbatore

Type

conf

DOI

10.1109/ICGCCEE.2014.6922293

Filename

6922293