Title :
Exposure and expulsion the soft errors in digital systems using redundancy techniques
Author :
Ilayaranimangammal, I. ; Palaniyappan, S. ; Vaishnavadevi, N.
Author_Institution :
VLSI Design, Shanmuganathan Eng. Coll., Pudukkottai, India
Abstract :
To disclose and removal the errors in the Flow chart of all the electronic systems using the tool RAPTOR. By analyzing the characteristics of Problem Analyzing Diagram and structured flowchart, and a structure identification and coding algorithm are put forward for structured flow diagram and PAD. Finally a integrated development platform is developed using such algorithms, including flowchart modeling, code automatic generation Fault tolerance technique using TMR for exposure and expulsion the soft errors in the digital systems. Faults are expose and eliminated without interrupting the normal functioning of the circuit. Single point of failure, is removal and implemented as a fault tolerant using a Triple Modular Redundancy (TMR). Conventional lockstep scheme uses duplication with comparison (DWC), the presence of fault is detected, but it fails to indicate the location of fault which is overcome in enriched lockstep by triple modular redundancy (TMR). TMR technique incorporates both temporary and permanent faults. The new intensifying lockstep scheme requires significantly shorter recovery time than conventional lock step. It uses significantly less number of slices.
Keywords :
flowcharting; program compilers; program diagnostics; software fault tolerance; DWC; PAD; RAPTOR; TMR; code automatic generation fault tolerance technique; coding algorithm; digital systems; duplication with comparison; lockstep scheme; problem analyzing diagram; redundancy techniques; soft errors; structure identification; structured flow diagram; structured flowchart; triple modular redundancy; Adders; Circuit faults; Digital systems; Fault tolerant systems; Redundancy; Testing; Tunneling magnetoresistance; Fault tolerance; Single-Event Upset (SEU); Triple Modular Redundancy (TMR); integrated development platform; problem analysis diagram; structured Flow chart;
Conference_Titel :
Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on
Conference_Location :
Coimbatore
DOI :
10.1109/ICGCCEE.2014.6922300