Low power D-latch design using MCML tri-state buffers

This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters. The power consumption of the proposed D-latch is compared with the D-latch designed using switched based MCML tri-state buffers which indicate that the proposed low power D-latch is power efficient. The simulation result also proves that the low power D-latch consumes 50% less efficient than the other D-latch.