Characterization & improvement of SNM in deep submicron SRAM design

Author

Singh, S.K. ; Singh, S.V. ; Kausik, B.K. ; Chauhan, C. ; Tripathi, T.

Author_Institution

Dept. of Electron. & Commun., IPEC, Ghaziabad, India

fYear

2014

fDate

20-21 Feb. 2014

Firstpage

538

Lastpage

542

Abstract

This paper examines the characteristics of static noise margin (SNM) of 6T SRAM Cell. The existing architectures of SRAM are first investigated, and after that a suitable basic 6T SRAM structure is selected. An analysis of the impact of parameters viz Cell ratio (CR), Pull up ratio (PR) and Supply voltage (+V_DD) on the SNM was carried out with a view to optimizing the performance of SRAM cell. It has been observed that the SNM increases with the increasing value of CR. Similarly with increase in value of PR, an increase in SNM was observed. Finally, Body biasing technique has been used to improve the SNM of 6T SRAM cell in 28nm technology at 25°C.

Keywords

SRAM chips; integrated circuit design; integrated circuit noise; 6T SRAM cell; SNM characterization; SNM improvement; body biasing technique; cell ratio; deep submicron SRAM design; pull up ratio; size 28 nm; static noise margin; supply voltage; temperature 25 degC; Computer architecture; Inverters; Microprocessors; Noise; SRAM cells; Transistors; CR; DRV; PR; SNM; SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Integrated Networks (SPIN), 2014 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-2865-1

Type

conf

DOI

10.1109/SPIN.2014.6777013

Filename

6777013