Design and implementation of FPGA based linear all digital phase-locked loop

This paper proposes a method of implementing a linear All Digital Phase Locked Loop (ADPLL) based on FPGA. The main emphasis is on the FPGA implementation of the digital PLL. All Digital Phase Locked Loop (ADPLL) model has been implemented using ISE Xilinx 9.2. The ADPLL is designed at the centre frequency of 100 kHz. The phase difference between two analytic signal is measured using a 16 bit pipelined CORDIC algorithm in vectoring mode. To remove the higher order harmonics of the error signals, PI controller based designing of the loop filter which has low pass behaviour is considered. To compute sinusoidal values for DDS, CORDIC algorithm in its rotation mode is used. The aim is to obtain high frequency resolution & short locking time in ADPLL.