DocumentCode
1178685
Title
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 
m CMOS
Author
Cao, Zhiheng ; Yan, Shouli ; Li, Yunchu
Author_Institution
Qualcomm, San Diego, CA
Volume
44
Issue
3
fYear
2009
fDate
3/1/2009 12:00:00 AM
Firstpage
862
Lastpage
873
Abstract
A 1.25 GS/s 6b ADC is implemented in a 0.13 mum digital CMOS process by time-interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 cycles. 5.5b ENOB at 1.25 GS/s and 5.8b ENOB at 1 GS/s are achieved without any off-line calibration, error correction or post processing. The entire ADC consumes 32 mW at 1.25 GS/s including T/H and reference buffers, and occupies 0.09 mm2 .
Keywords
CMOS analogue integrated circuits; analogue-digital conversion; digital CMOS process; frequency 2.5 GHz; internal clock frequency; CMOS analog integrated circuits; CMOS process; Calibration; Clocks; Energy consumption; Error correction; Frequency conversion; Low power electronics; Narrowband; Signal to noise ratio; Analog-to-digital conversion; CMOS analog integrated circuits; low-power electronics; switched-capacitor circuits;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2008.2012329
Filename
4787585
Link To Document