DocumentCode :
117876
Title :
Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash
Author :
Aslam, Chaudhry Adnan ; Yong Liang Guan ; Kui Cai
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
fYear :
2014
fDate :
9-12 Dec. 2014
Firstpage :
1
Lastpage :
9
Abstract :
NAND flash memory has been dominantly used in consumer electronic products ranging from hand-held phones to personal computers. However, the stored data in NAND flash memory is subject to several impairments such as Random Telegraph Noise (RTN), Cell-to-Cell Interference (CCI) and Data Retention Effect over time. In this paper, we focus on the RTN effect over flash memory cells which becomes even more serious as the memory approaches its lifetime. When the flash cells withstand increasingly large number of Program/Erase (P/E) operation, multiple interface traps are generated at tunnel oxide layer which results into large fluctuations in cell threshold voltage. These voltage fluctuations, in turn, degrade the system error performance. To tackle with this problem, we propose a simple yet effective system-level decoding scheme in which the memory cells are read multiple times to obtain threshold voltage fluctuations caused by RTN. Since each memory read operation produces a new realization of threshold voltage, we combine the read signal with LDPC extrinsic information. The performance improvements of our scheme are validated by computer simulation which shows that the lifetime of flash memory can be extended by more than 10K P/E cycles while maintaining bit-error-rate at 10-6 using NB-LDPC code over GF (4) with frame size N = 2272. This paper also presents the trade-off between performance improvement and extra memory sensing latency.
Keywords :
Galois fields; NAND circuits; error statistics; flash memories; parity check codes; random noise; CCI; Galois fields; MLC flash; NAND flash memory; RTN; bit error rate; cell threshold voltage; cell-to-cell interference; data retention effect; flash memory cells; multilevel cell flash; multiple interface traps; multiple memory reads; nonbinary LDPC code; program-erase operation; random telegraph noise; system level decoding scheme; threshold voltage fluctuations; Ash; Decoding; Detectors; Iterative decoding; Logic gates; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asia-Pacific Signal and Information Processing Association, 2014 Annual Summit and Conference (APSIPA)
Conference_Location :
Siem Reap
Type :
conf
DOI :
10.1109/APSIPA.2014.7041532
Filename :
7041532
Link To Document :
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