• DocumentCode
    1178856
  • Title

    Parallel simulated annealing: accuracy vs. speed in placement

  • Author

    Durand, M.D.

  • Author_Institution
    Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
  • Volume
    6
  • Issue
    3
  • fYear
    1989
  • fDate
    6/1/1989 12:00:00 AM
  • Firstpage
    8
  • Lastpage
    34
  • Abstract
    The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.<>
  • Keywords
    VLSI; circuit layout CAD; parallel algorithms; VLSI placement; accuracy; combining algorithms; connection Machine implementation; error measurements; local-memory implementation; parallel simulated annealing; parallelism; periodic synchronization; shared-memory implementation; speed; synchronization; task allocation; Circuit simulation; Computational modeling; Computer simulation; Costs; Optimization methods; Routing; Simulated annealing; Solids; Temperature; Tin;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.32410
  • Filename
    32410
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1178856