Title :
Scan design at NEC
Author :
Funatsu, Shigehiro ; Kawai, Masato ; Yamada, Akihiko
Author_Institution :
NEC Corp., Tokyo, Japan
fDate :
6/1/1989 12:00:00 AM
Abstract :
The authors describe scan path, NEC´s implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design and compare four implementations, including two scan-path techniques.<>
Keywords :
integrated circuit testing; logic testing; IC testing logic testing; design for testability; scan design approach; scan path; Automatic testing; Circuit faults; Circuit testing; Costs; Flip-flops; Logic testing; National electric code; System testing; Test pattern generators; Very large scale integration;
Journal_Title :
Design & Test of Computers, IEEE
