• DocumentCode
    1179448
  • Title

    Efficient Boolean manipulation with OBDD´s can be extended to FBDD´s

  • Author

    Gergov, Jordan ; Meinel, Christoph

  • Author_Institution
    Fachbereich IV-Inf., Trier Univ., Germany
  • Volume
    43
  • Issue
    10
  • fYear
    1994
  • fDate
    10/1/1994 12:00:00 AM
  • Firstpage
    1197
  • Lastpage
    1209
  • Abstract
    OBDD´s are the state-of-the-art data structure for Boolean function manipulation. Basic tasks of Boolean manipulation such as equivalence test, satisfiability test, tautology test and single Boolean synthesis steps can be performed efficiently in terms of fixed ordered OBDD´s. The bottleneck of most OBDD-applications is the size of the represented Boolean functions since the total computation merely remains tractable as long as the OBDD-representations remain of reasonable size. Since it is well known that OBDD´s are restricted FBDD´s (free BDD´s, i.e., BDD´s that test, on each path, each input variable at most once), and that FBDD-representations are often much more (sometimes even exponentially more) concise than OBDD-representations. We propose to work with a more general FBDD-based data structure. We show that FBDD´s of a fixed type provide, similar as OBDD´s of a fixed variable ordering, canonical representations of Boolean functions, and that basic tasks of Boolean manipulation can be performed in terms of fixed typed FBDD´s similarly efficient as in terms of fixed ordered OBDD´s. In order to demonstrate the power of the FBDD-concept we show that the verification of the circuit design for the hidden weighted bit function proposed Bryant can be carried out efficiently in terms of FBDD´s while this is, for principal reasons, impossible in terms of OBDD´s
  • Keywords
    Boolean functions; data structures; logic design; Boolean function manipulation; Boolean manipulation; OBDD; canonical representations; circuit design; data structure; equivalence test; satisfiability test; tautology test; total computation; Boolean functions; Circuit synthesis; Circuit testing; Data structures; Design optimization; Hardware design languages; Helium; Input variables; Logic; Performance evaluation;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.324545
  • Filename
    324545