Title :
40 Gbit/s limiting output buffer in 80 nm CMOS
Author :
Sialm, G. ; Kromer, C. ; Morf, T. ; Ellinger, F. ; Jäckel, H.
Author_Institution :
Electron. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
fDate :
9/15/2005 12:00:00 AM
Abstract :
A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 Ω load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation.
Keywords :
CMOS digital integrated circuits; buffer circuits; driver circuits; limiters; 1 V; 11 ps; 18 dB; 24 mW; 40 Gbit/s; 50 ohm; 660 mV; 80 nm; AC coupling; CMOS; buffer optimisation; limiting output buffer; power consumption;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20052172
