Title :
Low-jitter 10 GHz multiphase PLL in 90 nm CMOS
Author :
Kossel, M. ; Buchmann, P. ; Menolfi, C. ; Morf, T. ; Schmatz, M. ; Toifl, T. ; Weiss, J.
Author_Institution :
IBM Zurich Res. Lab., Ruschlikon, Switzerland
fDate :
9/15/2005 12:00:00 AM
Abstract :
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively.
Keywords :
CMOS integrated circuits; bootstrap circuits; jitter; microwave integrated circuits; phase locked loops; voltage-controlled oscillators; 10 GHz; 90 nm; CMOS integrated circuits; RMS jitter; bootstrap circuits; bootstrapped NMOS inverter oscillator; invertor oscillators; microwave integrated circuits; multiphase PLL; peak-to-peak jitter; phase locked loops; voltage-controlled oscillators;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20052306
