Title :
On polynomial-time testable combinational circuits
Author :
Rao, Nageswara S V ; Toida, Shunichi
Author_Institution :
Center for Eng. Syst. Adv. Res., Oak Ridge Nat. Lab., TN, USA
fDate :
11/1/1994 12:00:00 AM
Abstract :
The problems of identifying several nontrivial classes of Polynomial-Time Testable (PTT) circuits are shown to be NP-complete or harder. First, PTT classes obtained by using circuit decompositions proposed by Fujiwara (1988) and Chakradhar et al. (1990) are considered. Another type of decompositions, based on fanout-reconvergent (f-r) pairs, which also lead to PTT classes are proposed. The problems of obtaining these decompositions, and also some structurally similar general graph decompositions, are shown to be NP-complete or harder. Then, the problems of recognizing PTT classes formed by the Boolean formulae belonging to the weakly positive, weakly negative, bijunctive and affine classes are shown to be NP-complete
Keywords :
combinatorial circuits; computational complexity; fault location; logic testing; Boolean formulae; NP-completeness; PTT classes; affine classes; circuit decompositions; combinational circuits; fanout-reconvergent pairs; polynomial-time testable combinational circuits; stuck-at faults; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Helium; Polynomials; Power engineering and energy; Sequential circuits; System testing;
Journal_Title :
Computers, IEEE Transactions on