Serial array time slot interchangers and optical implementations

We consider time slot interchangers (TSIs) which are built from 2×2 exchange switches and delays and which are useful for time division multiplexed (TDM) systems in telecommunications and pipelined systems such as time multiplexed optical multiprocessors. We formulate a general method for constructing TSIs based on multistage interconnection networks in the space domain via space-to-time mapping. Two types of TSIs, time slot permuters and time slot sorters, are considered. We review the time slot permuter based on the Benes network, and obtain the Λ˜ time slot permuter based on the bit-controlled, self-routing Λ permutation network. The time slot sorter, S_N , is obtained from the Batcher spatial sorting network. The generalized Lambda time slot permuter Λ_N^q is obtained, in an algorithmic approach, by combining the idea of the Λ˜ time slot permuter and Q-way bitonic decomposition (Q=2 ^q). The numbers of switches, control complexities, and frame delays of these architectures are compared, and the problem of crosstalk in optical implementation is discussed. It is shown that control complexity can be traded against the number of switches