DocumentCode
1179718
Title
Reliable 2-bit/cell NVM technology using twin SONOS memory transistor
Author
Choi, B.Y. ; Park, B.-G. ; Lee, J.D. ; Shin, H. ; Lee, Y.K. ; Bai, K.H. ; Kim, D.-D. ; Kim, D.-W. ; Lee, C.-H. ; Park, D.
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
Volume
41
Issue
19
fYear
2005
fDate
9/15/2005 12:00:00 AM
Firstpage
1086
Lastpage
1087
Abstract
The twin SONOS memory (TSM) transistors for 2-bit/cell non-volatile-memory (NVM) application are presented and their reliability is evaluated so that they can be applied to next generation NVM technology. This new memory, which is implemented by the damascene gate and outer sidewall spacer processes, shows a high reliability down to 80 nm gate length.
Keywords
random-access storage; semiconductor-insulator-semiconductor devices; 2 bit; 2-bit cell NVM technology; damascene gate; nonvolatile-memory; twin SONOS memory transistor;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20052070
Filename
1512773
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