Design model and guidelines for n-well guard ring in epitaxial CMOS

This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guidelines have been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from the guard ring