DocumentCode
1181183
Title
System in Package Feasibility Process
Author
Stoppino, Pier Paolo ; Conci, Armando ; Lessio, Tito ; Ferrara, Davide
Author_Institution
Numonyx, Milan
Volume
97
Issue
1
fYear
2009
Firstpage
141
Lastpage
147
Abstract
This paper describes the procedure and the software process to verify the feasibility of a system in package. The process has been created to guarantee and ensure the main characteristics of such devices: a minimum time-to-market and great flexibility. A procedure is described for every step, starting from application definition to final electrical analysis. After a general introduction, all process design steps are technically analyzed; then each step of the final process check is described. Some comments and wishes are discussed in the conclusion.
Keywords
electronic engineering computing; integrated circuit design; system-in-package; electrical analysis; package feasibility process; process design steps; software process; system in package feasibility; time-to-market; Application software; Electronic design automation and methodology; Electronics packaging; Information analysis; Process design; Signal analysis; Signal generators; Software packages; System-on-a-chip; Time to market; Check; netlist; package design; parasitic;
fLanguage
English
Journal_Title
Proceedings of the IEEE
Publisher
ieee
ISSN
0018-9219
Type
jour
DOI
10.1109/JPROC.2008.2007475
Filename
4796276
Link To Document