Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology

Author

Chen, Tze Wee ; Chun, Jung-Hoon ; Lu, Yi-Chang ; Navid, Reza ; Wang, Wei ; Chen, Chang-Lee ; Dutton, Robert W.

Author_Institution

Center for Integrated Syst., Stanford Univ., Stanford, CA

Volume

56

Issue

4

fYear

2009

fDate

4/1/2009 12:00:00 AM

Firstpage

656

Lastpage

664

Abstract

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-mum three-dimensional (3-D)-SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D-SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D-SOI technology are also characterized and compared with conventional bulk CMOS technology.

Keywords

integrated circuit modelling; integrated circuit noise; integrated circuit packaging; silicon-on-insulator; 3D SOI technology; 3D packaging; device noise properties; electrothermal simulations; ring oscillators; size 0.18 mum; thermal modeling; CMOS technology; Circuit noise; Circuit optimization; Circuit simulation; Circuit testing; Electrothermal effects; Packaging; Phase noise; Ring oscillators; Semiconductor device modeling; 3-D silicon-on-insulator; Device noise; electrothermal; thermal modeling; three-dimensional (3-D) integrated circuit;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2009.2014188

Filename

4796307