An adaptive line equalizer VLSI using digital signal processing

Architecture and performance characteristics of an adaptive line equalizer VLSI needed to provide digital subscriber loop transmission at hundreds of kilobits per second are described. A wide automatic gain control (AGC) dynamic range and precise and quick adjustment are required for adaptive equalization. Considering these demands and advances in VLSI technology, a single-chip multiprocessor VLSI composed of a high-speed filtering processor, control processors, and a digital phase-locked loop (DPLL) has been developed using 1.5- mu m CMOS technology. The VLSI uses highly parallel processing, powerful instructions for equalization, and a rising edge detection DPLL. The chip can automatically equalize line loss of over 45 dB and cancel bridged-tap echoes up to four time slots after signal pulses at a 320-kb/s line bit rate.<>