High multiplication factor capacitor multiplier for an on-chip PLL loop filter

A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 A. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 m CMOS technology to employ the proposed capacitor multiplier.