DocumentCode :
1182026
Title :
Memory bandwidth saving by hardware tessellation with vertex shader
Author :
Chung, K. ; Yu, Chia-Hsiang ; Kim, Dongkyu ; Kim, Lee-Sup
Author_Institution :
Dept. of EECS, KAIST, Daejeon
Volume :
45
Issue :
5
fYear :
2009
Firstpage :
259
Lastpage :
260
Abstract :
Hardware architecture of a tessellator based on a vertex shader is proposed to save memory bandwidth for a mobile 3D graphics engine. According to the appropriate separation of the tessellation process, the powerful performance of a vertex shader, 120 Mvertices/s, is utilised for floating point computations. The remaining part of the process is handled by a dedicated control unit, implementation of which requires 6.2% additional logic gates. The proposed tessellator reduces the bandwidth consumed to transfer 3D geometry data up to 1/250.
Keywords :
computational geometry; computer graphics; floating point arithmetic; mobile computing; storage management; 3D geometry data; dedicated control unit; floating point computation; hardware tessellation; logic gate; memory bandwidth saving; mobile 3D graphics engine; vertex shader;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20092624
Filename :
4796352
Link To Document :
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