Passive equalizer design on high density interconnects for 25Gbps high speed IO and beyond

We propose a passive equalizer design on high density interconnects to improve the serial chip-to-chip communication channel performance. This new technique is a novel implementation and reinvention of the quarter-wave impedance transformer design originally adopted in the RF/microwave systems. By using narrow traces at early escaping routing and series of fat section impedance compensators at periodic λ/4 distances, this technique relies heavily on the signal wavelength of operating frequency and is suitable for specific high speed systems as required by PCIe, QPI, KTI, and SerDes for 25GHz and beyond. This technology utilizes the frequency-selective structures and has been tested on both microstrip and stripline routing of a flip-chip package design. Using proposed design optimization process for passive equalizer, we can maximize eye-opening and minimize inter-symbol interference in order to reduce data-dependent jitter. For 25Gbps differential high speed signaling, it shows over 3.1 dB improvement on differential return loss and over 0.7 dB improvement on differential insertion loss, which translate to over 17% increase on eye height and over 7% decrease of jitter for end-to-end whole channel simulation on server blade.