Efficient fault analysis in linear analog circuits

Fault analysis in analog networks is a form of network parameter identification. The problem of finding network parameters from measurements at the accessible terminals can be expressed as the solution of a system of nonlinear equations. Such a system of equations is usually solved by a multidimensional search. Every step of the search requires solving for the network responses in terms of the parameters, comparing the solution to the measured responses, and then adjusting the parameters in such a way as to produce a response closer to the measured response. The computation time required for this analysis is often excessive in practical applications, and poses a major impediment to fault analysis in analog circuits. The representation of short and open circuits poses additional problems, depending upon how the network equations are formulated. We have used nodal analysis representing short circuits by a change in the network graph, and open circuits by a zero branch admittance. A formula of Householder and sparse matrix techniques are used to efficiently compute the response of an electrical circuit with either a short circuit or other large parameter change. The number of complex multiplications and divisions to find the network response at the accessible terminals when the network has a single short circuit involving at least one inaccessible terminal is reduced by about a factor of 15 compared with direct methods.