Title :
CMOS ternary dynamic NORA logic
Author :
Herrfeld, A. ; Hentschke, S.
Author_Institution :
Kassel Univ.
fDate :
8/18/1994 12:00:00 AM
Abstract :
A new ternary dynamic NORA-technique TDN has been developed which needs neither a complex clocking scheme nor buffering between successive stages. The complete TDN circuits for a one-trit multiplier and a sum mod-3 operator are presented
Keywords :
CMOS integrated circuits; integrated logic circuits; multiplying circuits; summing circuits; ternary logic; CMOS ternary dynamic NORA logic; TDN circuits; one-trit multiplier; sum mod-3 operator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19940965
