Abstract :
Modeling can efficiently investigate the reliability of new packages, saving time, manpower, and cost for conducting actual tests; A good model is useful for short time-to-market. In this paper, only journal and technical magazine papers are reviewed, many of which report modeling analyses of single die and/or stacked die chip-scale packages. They are summarized regarding the methods, design parameters, and/or results. Brief comparisons are provided on similarities and differences of the effects of the common design parameters on solder-joint reliability. The effects of variations in materials, package designs, the number of dies, test conditions, and board geometry can be investigated efficiently by thermal cycling modeling or drop test modeling.
Keywords :
chip scale packaging; finite element analysis; integrated circuit modelling; integrated circuit reliability; soldering; board-level solder joint reliability modeling; chip-scale packages; drop test modeling; finite element techniques; package designs; single die CSP; stacked die CSP; thermal cycling modeling; Assembly; Chip scale packaging; Costs; Finite element methods; Integrated circuit modeling; Microelectronics; Power system reliability; Soldering; Testing; Wafer scale integration; Chip-scale packages (CSPs); critical solder joint locations; fatigue life; finite element analysis (FEA); modeling; single die CSPs; solder joint reliability; stacked die CSPs; system-in-package (SiP);
