Title :
MACTIS-A mask checking timing simulator
Author :
Kawamura, M. ; Hirabayashi, K.
fDate :
12/1/1980 12:00:00 AM
Abstract :
A new timing simulator is described for mask design verification of MOS/LSI before fabrication. Each circuit node is treated as the output of a multi-input transmission gate. Applying a macromodel technique to this transmission gate, it is possible to perform cost-effective timing simulation of the LS1 having up to 10 000 transistors.
Keywords :
Active networks; Multiport networks; Circuit simulation; Computational modeling; Data mining; Eigenvalues and eigenfunctions; Large scale integration; Reflection; Stability; Symmetric matrices; Timing; Variable structure systems;
Journal_Title :
Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCS.1980.1084758
