Chaotic encoder-decoder on FPGA for crypto system

Author

Roeksukrungrueang, Chanathip ; Dittaphong, Xaysamone ; Khongsomboon, Khamphong ; Panyanouyong, Nounchan ; Chivapreecha, Sorawat

Author_Institution

Dept. of Telecommun. Eng., King Mongkut´s Inst. of Technol. Ladkrabang, Bangkok, Thailand

fYear

2014

fDate

9-12 Dec. 2014

Firstpage

1

Lastpage

5

Abstract

An implementation of chaotic encoder-decoder on FPGA will be proposed in this paper. Overflow non-linearity by using 2\´s complement number in digital filter causes the phenomenon called "Chaos" in digital filter. An 1ER filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. Filter coefficients of both encoder and decoder can be compared to the secret key in private-key crypto system. However, if filter coefficients of chaotic decoder are not same as filter coefficients of chaotic encoder, ciphertext cannot decrypt to get original plaintext. Both chaotic encoder and decoder will be implemented on FPGA to demonstrate the hardware prototype of chaotic crypto system.

Keywords

FIR filters; IIR filters; chaos; cryptography; decoding; encoding; field programmable gate arrays; 2´s complement number; FIR filter; FPGA; IIR filter; chaos; chaotic crypto system; chaotic encoder; chaotic encoder-decoder; crypto system; digital filter; overflow nonlinearity; private-key crypto system; Chaos; Cryptography; Decoding; Field programmable gate arrays; Finite impulse response filters; IIR filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Asia-Pacific Signal and Information Processing Association, 2014 Annual Summit and Conference (APSIPA)

Conference_Location

Siem Reap

Type

conf

DOI

10.1109/APSIPA.2014.7041740

Filename

7041740