Title :
BiMOS transistors: merged bipolar/sidewall MOS transistors
Author :
O, Kenneth K. ; Reif, Rafael ; Lee, Hae-Seung
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible.<>
Keywords :
bipolar transistors; insulated gate field effect transistors; semiconductor technology; BiCMOS static memory cell; BiCMOS subcircuit elements; BiMOS transistors; NMOS-input BiMOS Darlington transistor; NMOS-input Darlington pair; PMOS-input BiMOS Darlington transistor; doping requirements; merged bipolar/sidewall MOS transistors; n-p-n bipolar transistor; BiCMOS integrated circuits; Bipolar transistors; Contacts; Doping; Equivalent circuits; Fabrication; Integrated circuit interconnections; MOSFETs; Wires;
Journal_Title :
Electron Device Letters, IEEE
