Design and implementation of fast FPGA based architecture for reversible watermarking

There are diverse hardware realization for digital watermarking of multimedia proposed in the literature. This paper focuses on the design and implementation of a fast FPGA(Field Programmable Gate Array) based architecture using reversible contrast mapping (RCM) based image watermarking algorithm. The specialty of this architecture attracts to the fact of clock-less encoder design and implementation which makes the design faster. The encoder module response time is independent of clock frequency, so the embedding of the watermark is possible as soon as the input is fetched. The schematic based design and implementation of the VLSI architecture have been done with Xilinx 14.1 on Spartan 3E FPGA family. The encoder requires 528 4-input LUTs and 303 slices. On the contrary, the decoder requires 613 LUTs and 347 slices. The maximum clock frequency of the decoder is 45 MHz. The results show the viability of low cost, high speed realtime use of the proposed VLSI architecture.