Spray coating process with polymer material for insulation in CIS-TSV wafer-level-packaging

This paper presents a novel spray coating process for the forming of sidewall insulation of through silicon via (TSV) which was a challenging process in CMOS image sensor (CIS) packaging. In conventional way, silicon oxide by plasma enhanced chemical vapor deposition (PECVD) is chosen as insulation material. In this paper, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via with the diameter of 75μm and depth of 100μm by novel spray coating process. To avoid the failure of TSV sidewall insulation and electrical interconnection characteristic, the thickness of polymer on the sidewall should be not less than 2μm. To achieve the insulation layer thickness target value, the temperature of spray coating process temperature was adjusted to control the viscosity of polymer. After the process optimization, the minimum thickness of sidewall polymer insulation layer is over 2.5μm meanwhile the conformal coverage characters of sidewall insulation layers are promoted.