DocumentCode :
118439
Title :
Solder joint fatigue life prediction in large size and low cost wafer-level chip scale packages
Author :
Ming-Che Hsieh ; Su-Lan Tzeng
Author_Institution :
Product & Technol. Marketing, STATS ChipPAC Taiwan Co., Ltd., Hsinchu, Taiwan
fYear :
2014
fDate :
12-15 Aug. 2014
Firstpage :
496
Lastpage :
501
Abstract :
With the highly insatiable demands of higher performance and lower cost requirements for handheld and portable electronic devices in the semiconductor industry, the wafer level chip scale package (WLCSP) is widely used in integrated circuit (IC) fabrication today with rapidly growing demands. Recently, WLCSP without utilization of an under-bump metallization (UBM) layer has been proposed for cost reduction purposes, eliminating the process of electroplating the UBM layer as compared to conventional WLCSP processes. For applications with larger than 5×5 mm2 die sizes, the die I/O can be increased to enhance the corresponding performance. With the increasing requirements of multifunctional, smaller form factor, lower cost and fine pitch package designs in WLCSPs, a number of challenges need to be overcome, especially in terms of preventing possible failures and enhancing reliability. It is well known that the empirical Coffin-Manson equation has been widely adopted to evaluate the thermal fatigue life of the solder joint in electronic packages. For the sake of understanding the thermal fatigue life of a large size and low cost WLCSP with Sn1.0Ag0.5Cu (SAC105) solder joints, the board level reliability (BLR) thermal cycling test (TCT) that follows JEDEC standards was evaluated. The solder joint characteristic life in a large size and low cost WLCSP can be obtained by Weibull analysis according to the experimental result. The three-dimensional (3D) finite element analysis (FEA) with rate dependent nonlinearity material properties was utilized to study the solder joint creep behaviors. With the correlation of experimental and simulation results, the modified Coffin-Manson equation for SAC105 solder joint fatigue life estimation in a large size and low cost WLCSP can be established. Based on the present equations, the thermal fatigue life for the utilization of SAC105 solder joints in a large size and low cost WLCSP can be effectively estimated through- the numerical modeling without any experimental evaluation. This study will be useful if high reliability and cost reduction in a large size and low cost WLCSP is required.
Keywords :
chip scale packaging; copper alloys; creep; electroplating; fine-pitch technology; finite element analysis; integrated circuit metallisation; integrated circuit reliability; silver alloys; solders; thermal stress cracking; tin alloys; wafer level packaging; 3D FEA; BLR; IC fabrication; JEDEC standards; SAC105 solder joint fatigue life estimation; SnAgCu; TCT; UBM layer; WLCSP; Weibull analysis; board level reliability; cost reduction; die I/O; die sizes; electronic packages; electroplating; empirical Coffin-Manson equation; fine pitch package designs; handheld electronic devices; integrated circuit fabrication; large size wafer-level chip scale packages; low cost wafer-level chip scale packages; numerical modeling; portable electronic devices; rate dependent nonlinearity material properties; reliability enhancement; semiconductor industry; smaller form factor; solder joint creep behaviors; solder joint fatigue life prediction; thermal cycling test; thermal fatigue life; three-dimensional finite element analysis; under-bump metallization layer; Conferences; Decision support systems; Electronics packaging; Three-dimensional displays; Coffin-Manson equation; Wafer level chip scale packages; board level reliability; finite element analysis; solder joint fatigue life; thermal cycling test;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology (ICEPT), 2014 15th International Conference on
Conference_Location :
Chengdu
Type :
conf
DOI :
10.1109/ICEPT.2014.6922704
Filename :
6922704
Link To Document :
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