Abstract :
This article introduces issues on the implementation of a front-end processor for Blu-ray disc (BD) recorder applications. This processor includes partial response maximum likelihood, a data processor block, and servo blocks. The nonlinear equalizer is designed to boost high-frequency signal components without increasing intersymbol interference. It can improve the quality of the high-frequency signal fed into the Viterbi detector, reduce jitter, and offer more tilt margins to the system. Due to the proposed nonlinear equalizer in PRML, less than 2 × 10/sup -4/ of the symbol error rate (SER), defined as the BD format book, is achieved with the tangential tilt margin of /spl plusmn/0.5/spl deg/. This system on a chip carries DP functions of a parity preserve/prohibit repeat minimum transition runlength (RMTR) (17PP) modem, Reed-Solomon (RS) codec, and buffer management. The Teaklite DSP is embedded for control functions such as focus servo, track servo, and auto calibration. It contains 12 million transistors in a 50 mm2 die, and is fabricated in 0.18 μm 1-poly 5-metal (1P5M) CMOS technology.
Keywords :
CMOS integrated circuits; Reed-Solomon codes; Viterbi detection; adaptive equalisers; error statistics; intersymbol interference; recorders; 50 mum; Blu-ray disc recorder; CMOS technology; Reed-Solomon codec; Viterbi detector; auto calibration; buffer management; data processor block; focus servo; front-end SOC; intersymbol interference; jitter reduction; nonlinear equalizer; partial response maximum likelihood; repeat minimum transition runlength; servo block; symbol error rate; track servo; CMOS technology; Detectors; Equalizers; Intersymbol interference; Jitter; Maximum likelihood detection; Servomechanisms; Signal design; System-on-a-chip; Viterbi algorithm;
