DocumentCode :
1184749
Title :
Design for autonomous test
Author :
McCluskey, Edward J. ; Bozorgui-nesbat, Saied
Volume :
28
Issue :
11
fYear :
1981
fDate :
11/1/1981 12:00:00 AM
Firstpage :
1070
Lastpage :
1079
Abstract :
A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible. Procedures for reconfiguring the existing registers into modified linear feedback shift registers (LFSR´s) which apply the exhaustive (not pseudorandom) test patterns or convert the responses into signatures are described. No fault models or test pattern generation programs are required. A method to modify CMOS circuits so that exhaustive testing can be used even when stuck-open faults must be detected is described. A detailed example using the 74181 ALU is presented.
Keywords :
CMOS integrated circuits, logic; Digital circuits; Digital system testing; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Integrated circuit testing; Military computing; Sequential analysis; System testing; Test pattern generators; Very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-4094
Type :
jour
DOI :
10.1109/TCS.1981.1084930
Filename :
1084930
Link To Document :
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