DocumentCode
1184866
Title
Chip level fault location using X-algorithm
Author
Jiang, H. ; Majithia, J.C.
Author_Institution
Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
Volume
141
Issue
5
fYear
1994
fDate
9/1/1994 12:00:00 AM
Firstpage
259
Lastpage
264
Abstract
In board level testing the faults are usually isolated to a field replacement unit (FRU) rather than to a single chip. In this paper a new algorithm, called the X-algorithm, is presented to locate a faulty chip in an FRU. The location patterns (LPs) which contain only one symbol X/X¯ are introduced. The trajectory of the X/X¯ propagation sensitises the faults in the FRU. Based on the test results the LPs can be generated easily. In the X-algorithm the X/X¯ propagation trajectory is analysed so that the faulty chip can be located automatically. Preliminary results show that the algorithm is quite effective, and it may not be necessary to exhaustively simulate with the LPs
Keywords
VLSI; fault location; logic testing; X-algorithm; chip level; fault location; faulty chip; field replacement unit; location patterns;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19941365
Filename
326787
Link To Document