DocumentCode
118520
Title
Modeling the bottom-up filling of through silicon vias with different additives
Author
Zuyang Wang ; Wei Luo ; Liming Gao ; Ming Li
Author_Institution
Inst. of Microelectron. Mater. & Technol., Shanghai Jiao Tong Univ., Shanghai, China
fYear
2014
fDate
12-15 Aug. 2014
Firstpage
618
Lastpage
621
Abstract
The superfilling of through silicon vias (TSVs) is a technical challenge for the fabrication of modern 3D Electronic packaging. In order to achieve void-free-filling for TSVs with different aspect ratios, various organic additives need to be added into the plating bath. Since TSV filling is a complex electrochemical and physical process, it is difficult and very time-consuming to get an optimal additive ratio through experiments. So, numerical simulation will play an important role in the optimization of vias filling. To explain the mechanism of void-free filling, different models have been developed recently. In this paper, a numerical model was built to simulate the electroplating process in different conditions. The arbitrary Lagrange-Eulerian (ALE) method for solving moving boundaries in Finite Element Method (FEM) was used for the simulation. Since the working mechanism of the additives is still not totally clear, the results in this study try to explain the roles of different additives qualitatively. The tool used in this experiment is Comsol Multiphysics, a commercial FEM software. The parameters used in this study are based on the experimental results or published literatures.
Keywords
additives; electroplating; finite element analysis; integrated circuit modelling; integrated circuit packaging; three-dimensional integrated circuits; 3D electronic packaging; ALE method; Comsol Multiphysics; FEM; TSV superfilling; arbitrary Lagrange-Eulerian method; aspect ratios; bottom-up filling modelling; commercial FEM software; complex physical process; electroplating process; finite element method; numerical model; numerical simulation; optimal additive ratio; organic additives; physical process; plating bath; through silicon vias; vias filling optimization; void-free-filling; Additives; Cathodes; Copper; Current density; Filling; Numerical models; Surface treatment; TSVs; additives; simulation; superfilling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Packaging Technology (ICEPT), 2014 15th International Conference on
Conference_Location
Chengdu
Type
conf
DOI
10.1109/ICEPT.2014.6922732
Filename
6922732
Link To Document