Linearization techniques for nth-order sensor models in MOS VLSI technology

The authors present new linearization techniques and introduce novel circuits for second- and third-order sensor models. Furthermore, a general framework as well as circuit techniques for linearization of sensor models of any order are presented. The new techniques are based on subtle circuit design of simple and compact multiplier/divider and vector multiplier circuits that comprise op-amps and MOS transistors. The design is programmable using DC control voltages and is capable of implementing different values of model parameters using identically sized devices without altering physical circuit layout. The resulting continuous-time signal processing circuits are completely compatible with MOS VLSI technology and easy to incorporate in a computer-aided design environment. The circuit design details are given and nonideal effects due to op-amp dynamics and MOS parasitic capacitances are investigated. Experimental results for the new second-order sensor models, obtained from a MOSIS 2-μm CMOS process test chip, and SPICE simulation results of third-order models verify the validity of the proposed linearization techniques