Expected value analysis of combinational logic networks

The results of an investigation into probabilistic analysis of combinational digital networks are reported herein. Basic gates as well as larger functional building blocks are assigned probability density functions in place of fixed input-output propagation delays. Signal lines interconnecting logic device models carry not I or 0 (binary) values, but rather continuous waveforms representing the expected values of these binary signals. Probabilistic models of the basic AND, OR, NOT, etc., gates are presented, as are methods for handling signal dependencies due to reconvergent fanout. Application of the models to reliability analysis is discussed.