DocumentCode
1185818
Title
Suppressing limit cycles in digital incremental computers
Author
Witten, Ian H. ; Mccrea, Philip G.
Volume
28
Issue
7
fYear
1981
fDate
7/1/1981 12:00:00 AM
Firstpage
723
Lastpage
730
Abstract
This correspondence examines the sources of limit cycle oscillations in Digital Incremental Computers and proposes several different methods for their suppression. A theoretical analysis is performed based on considering the effects of noise injected at the truncation points of the system and the results are verified by extensive simulation.
Keywords
DSP; Digital filter wordlength effects; Digital signal processing (DSP); Analytical models; Computational modeling; Computer errors; Difference equations; Digital filters; Hardware; Limit-cycles; Performance analysis; Refining; Transfer functions;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/TCS.1981.1085031
Filename
1085031
Link To Document