Improving floating-gate memory reliability by nanocrystal storage and pulsed tunnel programming

Nanocrystal memories have attracted considerable attentions in the last few years as one of the simplest evolution of the standard Flash technology allowing for improved reliability and scaling perspectives. The possibility for a significant thickness reduction for the oxides insulating the floating-gate layer in the memory cell is assured by the discrete storage effect, limiting the impact of stress-induced leakage current on data retention. In this paper we show at the array level that large improvements in anomalous cell occurrence after cycling is encountered for nanocrystal memories with thin tunnel oxide. Further improvements in array reliability is observed adopting a fast pulsed programming, limiting the defect generation rate by a proper definition of the programming waveform.