A detailed DVB-S2 receiver implementation: FPGA prototyping and preliminary ASIC resource estimation

Design and implementation of signal processing and synchronization algorithms for digital receivers are challenging tasks, especially concerning the verification phase that must cover as many functional tests as possible. This paper discloses the entire internal architecture of the receive chain of the ETSI DVB-S2 digital satellite communication standard and the methodology used for implementing it. It covers architectural, algorithm, and RTL design, together with laboratory setup, FPGA prototyping and VLSI resource estimation in 65nm CMOS. The result section demonstrates that our approach is able to synchronize and demodulate an 8-PSK DVB-S2 compliant signal, corrupted by all the impairments expected in a digital receiver.