Title :
A model for gate-oxide breakdown in CMOS inverters
Author :
Rodrìguez, R. ; Stathis, J.H. ; Linder, B.P.
Author_Institution :
Dept. d´´Enginyeria Electron., Univ. Autonoma de Barcelona, Bellaterra, Spain
Abstract :
The effect of oxide breakdown (BD) on the performance of CMOS inverters has been investigated. The results show that the inverter performance can be affected by the BD in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide BD conduction has been modeled as gate-to-diffusion leakage with a power-law formula of the type I=KV/sup p/, which was previously found to describe the BD in capacitor structures. This implies that the BD physics at oxide level is the same as that at circuit level.
Keywords :
CMOS digital integrated circuits; integrated circuit modelling; integrated circuit reliability; leakage currents; logic gates; semiconductor device breakdown; CMOS inverters; circuit level breakdown physics; gate-oxide breakdown model; gate-to-diffusion leakage; hard breakdown; inverter performance; leakage currents; oxide level breakdown physics; oxide reliability; partially depleted SOI technology; power-law formula; stress polarity; Dielectric breakdown; Digital circuits; Diodes; Electric breakdown; Inverters; Leakage current; Semiconductor device modeling; Silicon on insulator technology; Stress; Voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2002.808155
