Title :
A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures
Author :
Kotani, Hisakazu ; Akamatsu, Hironori ; Naito, Yasushi ; Fujii, Toyokazu ; Iwata, Tohru ; Tsuji, Toshiaki ; Itoh, Yutaka ; Shimizu, Norisato ; Hirase, Junji ; Shibata, Yoshiyuki ; Yamashita, Kazuhiro ; Hori, Takashi ; Fujita, Tsutomu
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fDate :
11/1/1994 12:00:00 AM
Abstract :
A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-μm CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz based on introducing (1) a suppressed High(H)-level differential data transfer scheme which ran be operated at 0.6 V, (2) a new pre-charge method which features a 1/2 VCC precharge level in read cycle and VSS pre-charge level in write cycle, and (3) a divided operation of array circuits for serial access
Keywords :
CMOS integrated circuits; DRAM chips; cinematography; integrated memory circuits; photographic materials; video recording; 0.25 mum; 0.6 V; 100 MHz; 256 Mbit/s; 256-Mb DRAM; 73 mA; CMOS technology; NMOS integrated circuits; VCC precharge level; array circuits; conventional circuit; moving picture storage; operating current; pre-charge method; read cycle; refresh-free-FIFO function; serial I/O ports; serial access; suppressed high level differential data transfer scheme; write cycle; Bandwidth; CMOS technology; Circuits; HDTV; Large-scale systems; Packaging; Random access memory; Senior members; Variable structure systems; Video recording;
Journal_Title :
Solid-State Circuits, IEEE Journal of
