Title :
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator
Author :
Nakamura, Kazuyuki ; Kuhara, Shigeru ; Kimura, Tohru ; Takada, Masahide ; Suzuki, Hisamitsu ; Yoshida, Hiroshi ; Yamazaki, Tohru
Author_Institution :
Microelectron. Res. Lab., NEC Corp., Kanagawa, Japan
fDate :
11/1/1994 12:00:00 AM
Abstract :
This 512 Kw×8 b×3 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator and a 0.4-μm BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Newly developed circuit technologies include: 1) a zig-zag double word-line scheme, 2) a centered bit-line load layout scheme, and 3) a phase-locked-loop (PLL) with a multistage-tapped ring oscillator which generates a clock cycle proportional pulse (CCPP) and a clock edge lookahead pulse (CELP)
Keywords :
BiCMOS integrated circuits; SRAM chips; clocks; oscillators; phase-locked loops; pipeline processing; timing circuits; 0.4 mum; 16 Mbit/s; 2-stage wave-pipeline scheme; 220 MHz; 220-MHz pipelined 16-Mb BiCMOS SRAM; BiCMOS process; GTL I/O interface; PLL proportional self-timing generator; PLL self-timing generator; centered bit-line load layout scheme; circuit technologies; clock cycle proportional pulse; clock edge lookahead pulse; fully-random read/write operations; multistage-tapped ring oscillator; phase locked loop; phase-locked-loop; synchronous BiCMOS SRAM; zig-zag double word-line scheme; BiCMOS integrated circuits; Clocks; Delay effects; Phase locked loops; Pipelines; Pulse circuits; Pulse generation; Random access memory; Registers; Synchronous generators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
