Title :
A high-performance SI memory cell
Author :
Leenaerts, D.M.W. ; Leeuwenburgh, A.J. ; Persoon, G.G.
Author_Institution :
Dept. of Electr. Eng., Tech. Univ. of Eindhoven, Netherlands
fDate :
11/1/1994 12:00:00 AM
Abstract :
In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to a high accuracy cell with measured errors less than 200 ppm for input currents between 50 and 85 μA. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies
Keywords :
CMOS integrated circuits; integrated memory circuits; switched networks; 50 to 85 muA; 700 ns; SI memory cell; design technique; differential error matching; high accuracy cell; high-performance memory cell; switched current memory cell; three phase clock cycle; Capacitance; Clocks; Current measurement; Helium; MOS devices; MOSFETs; Signal processing; Switches; Velocity measurement; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
