DocumentCode :
1187943
Title :
Energy-delay efficient test
Author :
Al-Yamani, A.A.
Author_Institution :
KFUPM, Dhahran
Volume :
1
Issue :
5
fYear :
2007
Firstpage :
653
Lastpage :
658
Abstract :
A technique that improves scan-shift speed by 60-100% through controlling power consumption during scan shift as shown by simulation results is presented. The technique exploits the quadratic relationship between power and voltage to significantly increase the scan-shift speed while staying within the same power budget constraints. The technique is also orthogonal to techniques that lower power consumption by controlling the activity ratio or gating the clock.
Keywords :
integrated circuit testing; power consumption; energy-delay efficient test; power budget constraints; power consumption; scan-shift speed;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt:20060227
Filename :
4312792
Link To Document :
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