Title :
Energy-delay efficient test
Author_Institution :
KFUPM, Dhahran
Abstract :
A technique that improves scan-shift speed by 60-100% through controlling power consumption during scan shift as shown by simulation results is presented. The technique exploits the quadratic relationship between power and voltage to significantly increase the scan-shift speed while staying within the same power budget constraints. The technique is also orthogonal to techniques that lower power consumption by controlling the activity ratio or gating the clock.
Keywords :
integrated circuit testing; power consumption; energy-delay efficient test; power budget constraints; power consumption; scan-shift speed;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt:20060227