Droop sensitivity of stuck-at fault tests

In nanometer-scale integrated circuits, simultaneous switching at gates in physical proximity may induce power supply droop, and thereby invoke timing faults, termed as droop faults. During at-speed testing of such chips, two test vectors in a test sequence may excite droop and, thus, cause test invalidation. Fast application of test vectors may be needed for high-speed testing or for built-in self-test systems. The occurrence of droop strongly depends on the sequence of test vectors applied. The effect of droop on fast testing of stuck-at faults is investigated. For combinational circuits, the droop sensitivity of a given test sequence is studied and a method of re-ordering to reduce this effect is proposed. Experimental results on benchmark circuits show that the increase in test length to achieve droop-insensitive re-ordering is low. Droop excitability in full-scan sequential circuits is also studied.