DocumentCode :
1187972
Title :
Design networks-on-chip with latency/ bandwidth guarantees
Author :
Lin, Shunjiang ; Su, Li ; Su, Hongye ; Zhou, Guoqing ; Jin, Di ; Zeng, Lang
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing
Volume :
3
Issue :
2
fYear :
2009
fDate :
3/1/2009 12:00:00 AM
Firstpage :
184
Lastpage :
194
Abstract :
A method is proposed to guarantee bandwidth (BW) or latency of network-on-chip. This method contains three kernels: traffic classification; flit-based switching; path pre-assignment and link-BW setting. Compared with the traditional circuit-switch method, the proposed method can guarantee the latency between one flit´s generation in the source node and its reception in the destination node. This method also supports a wide range of traffic types such as latency critical, low BW traffic and streaming data which only have BW requirement. Moreover, router and network interface which support the proposed method are implemented and a maximum latency formula is developed. Simulation and synthesis results show that this method can guarantee the BW and latency well and is relatively low cost.
Keywords :
circuit switching; logic design; network interfaces; network-on-chip; flit-based switching; link bandwidth setting; network interface; network-on-chip design; router; traffic classification;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
DOI :
10.1049/iet-cdt:20080036
Filename :
4799067
Link To Document :
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